1. Technical Field
The present invention relates to semiconductors and semiconductor manufacturing, and more particularly to employing hybrid orientation technology (HOT), and integrated devices on a hybrid orientated substrate.
2. Description of the Related Art
Hybrid Orientation Technology (HOT) provides an attractive scalability path for enhanced performance of complementary metal oxide semiconductors (CMOS) at and below the 45 nm technology node. By providing a substrate having regions of different crystal orientation, where each orientation is optimized for the mobility of a particular type of metal oxide semiconductor field effect transistor (MOSFET), significant improvements in overall performance may be achieved. Hybrid orientation technology takes advantage of the fact that pFET transistors operate best when fabricated on silicon with a (110) orientation, while nFET transistors operate best with a (100) orientation (the orientation of most substrates). For pFETs, hole mobility is 2.5 times higher on (110) surface orientation compared with that on a standard wafer with (100) surface orientation.
Several prior art approaches for achieving MOSFETs formed in different crystallographically oriented regions have been explored. For example, “High-Performance CMOS Fabricated on Hybrid Substrate with Different Crystal Orientations,” M. Yang, et al, IEEE IEDM, 2003 and “On the Integration of CMOS with Hybrid Crystal Orientations,” IEEE VLSI Tech Symposium, 2004), both provide a semiconductor substrate comprising distinct planar regions of different crystal orientation. Additionally, hybrid orientation technology has been described in the prior art, for example, in U.S. Pat. No. 6,815,278 to Leong et al. Leong et al. describes integrated semiconductor devices that are formed upon a silicon-on-insulator (SOI) substrate having different crystal orientations that provide optimal performance for a specific device. Another example includes U.S. Pat. No. 6,995,456 to Nowak.
Referring to FIG. 1, an integrated structure 10 using a conventional approach is illustratively shown. NMOS devices 12 are built on a (100) substrate 14 of a SOI wafer, and pMOS devices 16 are fabricated on a substrate which is grown from a carrier substrate 18 with (110) orientation. Defect zones 20 are found at edges of the opening for epitaxial growth. These defect zones 20 occupy a high percentage of valuable real estate. This method becomes impractical for CMOS circuits where 50% of the area is formed by PMOS devices which are mingled with the NMOS devices. The waste area is roughly estimated to be from 10% to 25%.
The prior art fails to address, among other things, the specific classes of defects that arise due to the specific methods of fabricating hybrid orientation silicon substrates. Furthermore, the means for detecting, modeling, and reducing such defects during the mass manufacturing of such structures is neglected.
Most of the previously published methods for fabricating hybrid orientation substrates and those under development today involve bonding two silicon wafers with different crystal orientations to form an upper silicon layer with a first crystal orientation on a lower silicon substrate with a second crystal orientation, removing a portion of the upper silicon layer, and epitaxially re-growing silicon from the lower silicon substrate. Such an approach has several disadvantages, among which the severe defect issue prevents the hybrid orientation technology from being successfully adopted in mass production. Data has consistently shown that a large number of defects are undesirably formed during the epitaxial growth process.
Although most of these defects are localized at the interface between the two differently crystal-oriented regions and therefore can be eliminated in a subsequent isolation structure 22 formation process (e.g., shallow trench isolation (STI), some defects propagate into the re-grown region where active devices are formed. Interface defects and defects propagating into the epi re-grown regions are commonplace in prior art devices.
These above-mentioned defects in the epi regions have detrimental effects on device performance and reliability. Devices fabricated with a prior art hybrid orientation technology suffer increased gate oxide leakage due to propagated crystal defects in (110) oriented epi grown PFETs compared with devices fabricated without hybrid orientation technology.